Novel Arithmetic and Logic Unit Design for Robust Cryptographic Protocols

Abstract

Today, modern communication is heavily dependent on cryptographic protocols, due to which their robustness in adversarial conditions remains an active research topic. In the past, the security of any cryptography algorithm was thoroughly investigated against noninvasive attacks. However, invasive attacks are becoming particularly pertinent for current and future technologies. This work presents a reliable processing unit for cryptographic protocols with distributed self-checking ability. The proposed design can not only detect the fault but can also determine the location of its occurrence. Since an adder is a vital component in cryptography because it is used for addition and modular exponentiation, which is the main component of secret key generation. Therefore, we proposed self-checking architectures for a wide variety of commonly used adders, whereas self-checking logic gates are designed using pass transistor-based low area double modular redundancy. The key generation is the most sensitive task in cryptography, which must be secure for reliable communication. Therefore, we proposed a self-checking hardware design for the Montgomery multiplier (MM), which can counter multiple faults simultaneously. The proposed 64-bit self-checking MM approach with distributed fault prognosis mechanism requires 84.8% area and 73.5% power overhead compared to the non-self-checking design. Moreover, it has been observed that the area exhibits a decreasing trend with the size of the multiplier, which means that area overhead will further reduce for higher data size.

Date of Award	2023
Original language	American English
Awarding Institution	HBKU College of Science and Engineering