TY - GEN
T1 - VLSI implementation of hard- and soft-output sphere decoding for wide-band MIMO systems
AU - Studer, Christoph
AU - Wenk, Markus
AU - Burg, Andreas
N1 - Publisher Copyright:
© IFIP International Federation for Information Processing 2012.
PY - 2012
Y1 - 2012
N2 - Multiple-input multiple-output (MIMO) technology in combination with orthogonal frequency-division multiplexing (OFDM) is the key to meet the demands for data rate and link reliability of modern wide-band wireless communication systems, such as IEEE 802.11n or 3GPP-LTE. The full potential of such systems can, however, only be achieved by high-performance data-detection algorithms, which typically exhibit prohibitive computational complexity. Hard-output sphere decoding (SD) and soft-output single tree-search (STS) SD are promising means for realizing high-performance MIMO detection and have been demonstrated to enable efficient implementations in practical systems. In this chapter, we consider the design and optimization of register transfer-level implementations of hard-output SD and soft-output STS-SD with minimum area-delay product, which are well-suited for wide-band MIMO systems. We explain in detail the design, implementation, and optimization of VLSI architectures and present corresponding implementation results for 130 nm CMOS technology. The reported implementations significantly outperform the area-delay product of previously reported hard-output SD and soft-output STS-SD implementations.
AB - Multiple-input multiple-output (MIMO) technology in combination with orthogonal frequency-division multiplexing (OFDM) is the key to meet the demands for data rate and link reliability of modern wide-band wireless communication systems, such as IEEE 802.11n or 3GPP-LTE. The full potential of such systems can, however, only be achieved by high-performance data-detection algorithms, which typically exhibit prohibitive computational complexity. Hard-output sphere decoding (SD) and soft-output single tree-search (STS) SD are promising means for realizing high-performance MIMO detection and have been demonstrated to enable efficient implementations in practical systems. In this chapter, we consider the design and optimization of register transfer-level implementations of hard-output SD and soft-output STS-SD with minimum area-delay product, which are well-suited for wide-band MIMO systems. We explain in detail the design, implementation, and optimization of VLSI architectures and present corresponding implementation results for 130 nm CMOS technology. The reported implementations significantly outperform the area-delay product of previously reported hard-output SD and soft-output STS-SD implementations.
KW - MIMO-OFDM communication systems
KW - Single tree-search (STS) SD algorithm
KW - Sphere decoding (SD)
KW - VLSI implementation
UR - https://www.scopus.com/pages/publications/84902358548
U2 - 10.1007/978-3-642-28566-0_6
DO - 10.1007/978-3-642-28566-0_6
M3 - Conference contribution
AN - SCOPUS:84902358548
SN - 9783642285653
T3 - IFIP Advances in Information and Communication Technology
SP - 128
EP - 154
BT - VLSI-SoC
A2 - Ayala, Jose L.
A2 - Alonso, David Atienza
A2 - Reis, Ricardo
PB - Springer New York LLC
T2 - 18th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2010
Y2 - 27 September 2010 through 29 September 2010
ER -