@inproceedings{eaeca03ec3b3433791f1b4a3411d193a,
title = "VLSI implementation of a low-complexity LLL lattice reduction algorithm for MIMO detection",
abstract = "Lattice-reduction (LR)-aided successive interference cancellation (SIC) is able to achieve close-to optimum error-rate performance for data detection in multiple-input multiple-output (MIMO) wireless communication systems. In this work, we propose a hardware-efficient VLSI architecture of the Lenstra-Lenstra-Lov{\'a}sz (LLL) LR algorithm for SIC-based data detection. For this purpose, we introduce various algorithmic modifications that enable an efficient hardware implementation. Comparisons with existing FPGA implementations show that our design outperforms state-of-the-art LR implementations in terms of hardware-efficiency and throughput. We finally provide reference ASIC implementation results for 130 nm CMOS technology.",
author = "L. Bruderer and C. Studer and M. Wenk and D. Seethaler and A. Burg",
year = "2010",
doi = "10.1109/ISCAS.2010.5537742",
language = "English",
isbn = "9781424453085",
series = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems",
publisher = "IEEE Computer Society",
pages = "3745--3748",
booktitle = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems",
address = "United States",
note = "2010 IEEE International Symposium on Circuits and Systems, ISCAS 2010 ; Conference date: 30-05-2010 Through 02-06-2010",
}