Synchronous Bus Arbitration with Constant Logic Per Module

Hussein M. Alnuweiri

doi:10.1109/ipps.1994.288321

Synchronous Bus Arbitration with Constant Logic Per Module

Hussein M. Alnuweiri^*

^*Corresponding author for this work

University of British Columbia

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A novel technique for distributed synchronous bus arbitration is presented in this paper. The proposed scheme is based on two orthogonal arbitration functions, one that employs bounded-weight binary codes, and another that employs unitary codes. This scheme trades off bus-width with arbitration-time and arbitration logic per device, such that both arbitration time and arbitration logic (per device) can be reduce by increasing bus width. Alternatively, this method allows the number of devices connected to a bus to be increased without changing the arbitration logic of each device (or the number of arbitration steps)., only the width of the arbitration bus must be increased in this case.

Original language	English
Title of host publication	Proceedings of 8th International Parallel Processing Symposium, IPPS 1994
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	35-41
Number of pages	7
ISBN (Electronic)	0818656026, 9780818656026
DOIs	https://doi.org/10.1109/ipps.1994.288321
Publication status	Published - 6 Aug 2002
Externally published	Yes
Event	8th International Parallel Processing Symposium, IPPS 1994 - Cancun, Mexico Duration: 26 Apr 1994 → 29 Apr 1994

Publication series

Name	Proceedings of 8th International Parallel Processing Symposium, IPPS 1994

Conference

Conference	8th International Parallel Processing Symposium, IPPS 1994
Country/Territory	Mexico
City	Cancun
Period	26/04/94 → 29/04/94

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10.1109/ipps.1994.288321

Cite this

@inproceedings{f3c113464e964b57b7a2337ba54efd59,

title = "Synchronous Bus Arbitration with Constant Logic Per Module",

abstract = "A novel technique for distributed synchronous bus arbitration is presented in this paper. The proposed scheme is based on two orthogonal arbitration functions, one that employs bounded-weight binary codes, and another that employs unitary codes. This scheme trades off bus-width with arbitration-time and arbitration logic per device, such that both arbitration time and arbitration logic (per device) can be reduce by increasing bus width. Alternatively, this method allows the number of devices connected to a bus to be increased without changing the arbitration logic of each device (or the number of arbitration steps)., only the width of the arbitration bus must be increased in this case.",

author = "Alnuweiri, \{Hussein M.\}",

note = "Publisher Copyright: {\textcopyright} 1994 IEEE.; 8th International Parallel Processing Symposium, IPPS 1994 ; Conference date: 26-04-1994 Through 29-04-1994",

year = "2002",

month = aug,

day = "6",

doi = "10.1109/ipps.1994.288321",

language = "English",

series = "Proceedings of 8th International Parallel Processing Symposium, IPPS 1994",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "35--41",

booktitle = "Proceedings of 8th International Parallel Processing Symposium, IPPS 1994",

address = "United States",

}

Alnuweiri, HM 2002, Synchronous Bus Arbitration with Constant Logic Per Module. in Proceedings of 8th International Parallel Processing Symposium, IPPS 1994. Proceedings of 8th International Parallel Processing Symposium, IPPS 1994, Institute of Electrical and Electronics Engineers Inc., pp. 35-41, 8th International Parallel Processing Symposium, IPPS 1994, Cancun, Mexico, 26/04/94. https://doi.org/10.1109/ipps.1994.288321

Synchronous Bus Arbitration with Constant Logic Per Module. / Alnuweiri, Hussein M.
Proceedings of 8th International Parallel Processing Symposium, IPPS 1994. Institute of Electrical and Electronics Engineers Inc., 2002. p. 35-41 (Proceedings of 8th International Parallel Processing Symposium, IPPS 1994).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Synchronous Bus Arbitration with Constant Logic Per Module

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