Robust intermediate read-out for deep submicron technology CMOS image sensors

In this paper, a CMOS image sensor featuring a novel spiking pixel design and a robust digital intermediate read-out is proposed for deep submicron CMOS technologies. The proposed read-out scheme exhibits a relative insensitivity to the ongoing aggressive scaling of the supply voltage. It is based on a novel compact spiking pixel circuit, which combines digitizing and memory functions. Illumination is encoded into a Gray code using a very simple yet robust Gray 8-bit counter memory. Circuit simulations and experiments demonstrate the successful operation of a 64 × 64 image sensor, implemented in a 0.35 μm CMOS technology. A scalability analysis is presented. It suggests that deep sub-0.18 μm will enable the full potential of the proposed Gray encoding spiking pixel. Potential applications include multiresolution imaging and motion detection.