On the design of the fractional-order sigma-delta modulators with ELD compensation

This work introduces a new type of continuous-time sigma-delta modulation (CTSDM) system by converting one of the integrators in the sigma-delta loop to the fractional-order domain. This approach unleashed new benefits, such as enabling band-pass SDM architectures without needing higher-order integrators in the loop. An 8-bit BP-CTSDM is designed and verified on FPAA. The sensitivity analysis showed linear dependency of the fractional-order filter poles to passives with a factor of. This could be mitigated by designing using wider poles or by means of a trimming technique. Also, it is found that the fractional-order modulators have a higher input signal range compared to the integer-order counterparts and lower static loss. Since the fractional-order shift is one of the unique properties of fractional-order filters, these filters are the best fit for excess loop delay (ELD) compensation. Detailed analysis is introduced, showing that one can compensate for excess delays in the loop without needing extra circuitry or branches with the right choice of fractional order. A simple 5-bit SDM with ELD is implemented and verified on FPAA to prove the theory. Simulink and FPAA match the theoretical analysis.