Lower-power TSPC-based domino logic circuit design with 2/3 clock load

Keyphrases

• True Single Phase Clock 100%
• Logic Circuit Design 100%
• Domino Logic Circuits 100%
• 45 Nm CMOS Technology 33%
• Load Capacitance 33%
• Conventional Design 33%
• 90-nm CMOS Technology 33%
• Keeper 33%
• Charge Sharing 33%
• Power Saving 33%
• Clock Distribution Network 33%

Engineering

• Logic Input 100%
• Logic Design 100%
• Clock Distribution Networks 50%
• Load Capacitance 50%