@inproceedings{1ab15eb8e2df43d2ab2329c9c94f7c80,
title = "Incremental Delta-Sigma ADC with Reduced Conversion Cycles via Quantization-Skip",
abstract = "This paper presents a technique to effectively reduce the number of conversion cycles of the 1st-order incremental delta-sigma data converter (IADC1). Typically, an IADC1 requires 2N cycles to achieve N-bit resolution if using a sinc1 filter for reconstruction. The proposed quantization-skip technique can effectively reduce the average conversion cycles and, therefore, the energy consumption of an IADC1. Specifically, during conversion, the quantizer output is predicted using the previous bitstream pattern to achieve automatic bitstream fill-in without analog domain operations. Behavioral level simulations show that this technique can reduce the conversion cycles by 24\% on average (maximum reduction of ∼50\%) with little digital overhead.",
keywords = "bitstream fill-in, IADC, Incremental delta-sigma ADC, quantization-skip",
author = "Amgad Ghonem and Amine Bermak and Bo Wang",
note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 ; Conference date: 25-05-2025 Through 28-05-2025",
year = "2025",
month = may,
day = "28",
doi = "10.1109/ISCAS56072.2025.11044181",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings",
address = "United States",
}