Abstract
FPGA-based computing systems provide a feasible and cost-effective platform for implementing fast parallel arithmetic circuits for digital signal and image processing. This paper reports the results obtained from embedding a highly parallel convolution algorithm on an FPGA-based 'transformable' computer. Such a computer is intended to serve as a transformable co-processor for a standard microprocessor system. However, the transformable co-processor is reconfigurable and is capable of exploiting the concurrency of computations more than the 'sequential' microprocessor. Our experiments show that a significant gain in speed can be achieved by using the transformable co-processor. We present an example of performing a sequence of (independent) 16-point convolutions on 8-bit data, and show that the speed factor improves significantly as the number of convolutions to be performed increases.
| Original language | English |
|---|---|
| Pages (from-to) | 197-203 |
| Number of pages | 7 |
| Journal | IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings |
| Publication status | Published - 1995 |
| Externally published | Yes |
| Event | Proceedings of the 1995 IEEE Symposium on FPGAs for Custom Computing Machines - Napa Valley, CA, USA Duration: 19 Apr 1995 → 21 Apr 1995 |