DROPc-Dynamic Resource Optimization for Convolution Layer

The computational complexity of convolutional neural networks (CNNs) becomes challenging for resource-constrained hardware devices. The convolution layer is predominant in the overall CNN architecture, performing the expensive multiplication and accumulation operation. Therefore, designing a hardware-efficient convolution layer will effectively improve the overall performance of a CNN. In this research, we propose a dynamic resource optimization (DROP) approach to improve the power and delay of the convolution layer. The proposed approach controls the computational path in accordance to the interrupts which are dependent on a non-zero-bit pattern. With a single interrupt, our solution provides 42.5% power and 36.7% delay efficiency compared to the standard bit-serial-parallel approach. Moreover, the power consumed by eight parallel functioning blocks is 27.7% less than the traditional bit-parallel approach.