TY - GEN
T1 - Digital VLSI implementation of a multi-precision neural network classifier
AU - Bermak, Amine
AU - Martinez, Dominique
N1 - Publisher Copyright:
© 1999 IEEE.
PY - 1999
Y1 - 1999
N2 - A systolic multi-precision digital VLSI classifier referred to as "SysNeuro" is presented. Unlike the usual VLSI implementation of classifiers, this hardware has been designed to achieve variable precision computations. A hardware reconfiguration is obtained by using switch elements to change the hardware connection between adjacent 4 bit neuron building blocks. With this reconfiguration concept it is possible to either increase the precision by pooling together adjacent cells or to increase the number of neurons for low levels of precision. Moreover, the design is easily programmable and can be configured to any artificial neural network (ANN) topology in order to cover various kinds of application. The chip integrates 16/8/4 neurons with a corresponding precision of 4/8/16 bits. A prototype has been successfully realized using 0.7 μm CMOS technology.
AB - A systolic multi-precision digital VLSI classifier referred to as "SysNeuro" is presented. Unlike the usual VLSI implementation of classifiers, this hardware has been designed to achieve variable precision computations. A hardware reconfiguration is obtained by using switch elements to change the hardware connection between adjacent 4 bit neuron building blocks. With this reconfiguration concept it is possible to either increase the precision by pooling together adjacent cells or to increase the number of neurons for low levels of precision. Moreover, the design is easily programmable and can be configured to any artificial neural network (ANN) topology in order to cover various kinds of application. The chip integrates 16/8/4 neurons with a corresponding precision of 4/8/16 bits. A prototype has been successfully realized using 0.7 μm CMOS technology.
UR - https://www.scopus.com/pages/publications/84964548223
U2 - 10.1109/ICONIP.1999.845655
DO - 10.1109/ICONIP.1999.845655
M3 - Conference contribution
AN - SCOPUS:84964548223
T3 - ICONIP 1999, 6th International Conference on Neural Information Processing - Proceedings
SP - 560
EP - 565
BT - ICONIP 1999, 6th International Conference on Neural Information Processing - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 6th International Conference on Neural Information Processing, ICONIP 1999
Y2 - 16 November 1999 through 20 November 1999
ER -