Design and implementation of high-speed arbiter for large scale VOQ crossbar switches

Crossbars are frequently used as the switching fabric for high-performance packet switches (IP routers, ATM switches, Ethernet switches). The performance, functionality, and scalability (in terms of line rate and/or number of ports) of these switches are directly related to the arbitration/scheduling algorithm which must retrieve the state information of input queues, compute a (pseudo-) optimum matching, and configure the crossbar accordingly, all within one packet cycle. In this paper, we give a detailed hardware design and implementation of a novel arbitration scheme, named RDSRR [1], that lends itself well to high-speed implementation, while at the same time achieves excellent performance under a variety of traffic patterns. We present a novel pipeline technique and the full-custom design of the arbiter circuit using TSMC 0.25 m CMOS technology which can support switch sizes of up to 256 × 256 at a line rate of 10 Gbps.