Bandwidth availability of m-level hierarchical multiprocessor systems

In previous work, we proposed an m-level hierarchical multiprocessor system. The proposed system reduces the network complexity by employing m levels of hierarchy. The system performance was analyzed, and the results showed that, for a higher rate of local requests, the system performed close to the crossbar system, and better than a typical multiple-bus system (with the number of buses equal to half the number of processors). In this paper, we study the effect of failures on the performance of the m-level hierarchical multiprocessor systems. We develop analytical modeling techniques to compute the reliability and the bandwidth availability of the m-levelsystem, for hierarchically nonuniform reference (HNR) and uniform reference (UR) models. The results obtained for the m-level system are compared with those of the crossbar and multiple-bus systems.