An ultra-low power operating technique for mega-pixels current-mediated CMOS imagers

A novel ultra-low power operating technique is presented for Mega-pixels current-mediated CMOS imagers. In the proposed technique, the reset and read-out phases occur simultaneously: as a single pixel is being read-out another pixel is being reset. Such a strategy reduces power consumption by more than 2 orders of magnitude for current-mediated Mega-pixels CMOS imagers, while still allowing for on-read-out fixed pattern noise correction. Power consumption becomes independent of both read-out speed and imager array size. Additionally, the proposed operating technique leads to improved linearity for the pixel response, increased dynamic range as well as on-chip digital shutter functionality. A single additional address decoder is required to generate the reset signals, resulting in a marginal increase in silicon area. The wiring overhead is kept to a minimum with only a single control signal required to operate the current-mediated CMOS imager.