Abstract
This paper describes a hardware implementation of tree classifiers based on a custom VLSI chip and a CPLD chip. The tree classifier comprises a first layer of threshold logic unit, implemented on a reconfigurable custom chip, followed by a logical function implemented using a CPLD chip. We first describe the architecture of tree classifiers and compare its performance with support vector machine (SVM) for different data sets. The reconfigurability of the hardware (number of classifiers, topology and precision) is discussed. Experimental results show that the hardware presents a number of interesting feature such as reconfigurability, as well as improved fault tolerance.
| Original language | English |
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| Pages | A32-A35 |
| Publication status | Published - 2004 |
| Externally published | Yes |
| Event | IEEE TENCON 2004 - 2004 IEEE Region 10 Conference: Analog and Digital Techniques in Electrical Engineering - Chiang Mai, Thailand Duration: 21 Nov 2004 → 24 Nov 2004 |
Conference
| Conference | IEEE TENCON 2004 - 2004 IEEE Region 10 Conference: Analog and Digital Techniques in Electrical Engineering |
|---|---|
| Country/Territory | Thailand |
| City | Chiang Mai |
| Period | 21/11/04 → 24/11/04 |