TY - GEN
T1 - A PWM DPS with pixel-level reconfigurable 4/8-bit counter/SRAM
AU - Yung, Yat Fong
AU - Bermak, Amine
PY - 2005
Y1 - 2005
N2 - In this paper, a pulse width modulation (PWM) digital pixel sensor (DPS) is presented. The pixel includes a novel pixel-level reconfigurable 4/8-bit counter/SRAM, which can operate as a 4-bit counter or as an 8-bit memory. In contrast to the conventional PWM DPS in which all the encoding data are provided by a global counter, in our DPS, for the 8-bit digital data encoding the photodiode current, 4 bits are obtained from this pixel-level counter and the other 4 bits are provided by a global counter. The number of global data buses is thus reduced which in turn reduces the global bus capacitance and ease the routing. Moreover, the pixel can operate in 8-bit or in 4-bit conversion mode. 8-bit conversion provides a normal high resolution imaging while 4-bit conversion provides a higher frame rate. The pixel sensor has been designed and fabricated in a 0.35μm CMOS technology and its operation will be demonstrated through experimental results. Each pixel occupies an area of 46μm × 48μm with a fill-factor of 14%.
AB - In this paper, a pulse width modulation (PWM) digital pixel sensor (DPS) is presented. The pixel includes a novel pixel-level reconfigurable 4/8-bit counter/SRAM, which can operate as a 4-bit counter or as an 8-bit memory. In contrast to the conventional PWM DPS in which all the encoding data are provided by a global counter, in our DPS, for the 8-bit digital data encoding the photodiode current, 4 bits are obtained from this pixel-level counter and the other 4 bits are provided by a global counter. The number of global data buses is thus reduced which in turn reduces the global bus capacitance and ease the routing. Moreover, the pixel can operate in 8-bit or in 4-bit conversion mode. 8-bit conversion provides a normal high resolution imaging while 4-bit conversion provides a higher frame rate. The pixel sensor has been designed and fabricated in a 0.35μm CMOS technology and its operation will be demonstrated through experimental results. Each pixel occupies an area of 46μm × 48μm with a fill-factor of 14%.
UR - https://www.scopus.com/pages/publications/34548812395
U2 - 10.1109/ISCAS.2005.1464947
DO - 10.1109/ISCAS.2005.1464947
M3 - Conference contribution
AN - SCOPUS:34548812395
SN - 9780780388345
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1754
EP - 1757
BT - Proceedings - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2005 IEEE International Symposium on Circuits and Systems, ISCAS 2005
Y2 - 23 May 2005 through 26 May 2005
ER -