A novel scalable spiking pixel architecture for deep submicron CMOS technologies

Farid Boussaid; Chen Shoushun; Amine Bermak

doi:10.1109/dtis.2006.1708718

A novel scalable spiking pixel architecture for deep submicron CMOS technologies

Farid Boussaid^*, Chen Shoushun, Amine Bermak

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

In this paper, we propose a scalable spiking pixel architecture for deep submicron CMOS technologies. The proposed pixel architecture uniquely combines counting and memory functions into a single compact circuit, providing for in-pixel storage capability, in-pixel analog-to-digital conversion and random read-out of digital pixel values. Pixel fill-factor is better than 15% for a 50×50μm pixel fabricated using AMI 0.35μm CMOS technology. Reported experimental results validate the proposed spiking pixel architecture for the next generation of deep submicron silicon processes.

Original language	English
Title of host publication	Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006
Publisher	IEEE Computer Society
Pages	131-135
Number of pages	5
ISBN (Print)	0780397266, 9780780397262
DOIs	https://doi.org/10.1109/dtis.2006.1708718
Publication status	Published - 2006
Externally published	Yes

Publication series

Name	Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006

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Boussaid, F., Shoushun, C., & Bermak, A. (2006). A novel scalable spiking pixel architecture for deep submicron CMOS technologies. In Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006 (pp. 131-135). Article 1708718 (Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006). IEEE Computer Society. https://doi.org/10.1109/dtis.2006.1708718

Boussaid, Farid ; Shoushun, Chen ; Bermak, Amine. / A novel scalable spiking pixel architecture for deep submicron CMOS technologies. Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006. IEEE Computer Society, 2006. pp. 131-135 (Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006).

@inproceedings{bac3add98002492c90c346d6a011f7f6,

title = "A novel scalable spiking pixel architecture for deep submicron CMOS technologies",

abstract = "In this paper, we propose a scalable spiking pixel architecture for deep submicron CMOS technologies. The proposed pixel architecture uniquely combines counting and memory functions into a single compact circuit, providing for in-pixel storage capability, in-pixel analog-to-digital conversion and random read-out of digital pixel values. Pixel fill-factor is better than 15\% for a 50×50μm pixel fabricated using AMI 0.35μm CMOS technology. Reported experimental results validate the proposed spiking pixel architecture for the next generation of deep submicron silicon processes.",

author = "Farid Boussaid and Chen Shoushun and Amine Bermak",

year = "2006",

doi = "10.1109/dtis.2006.1708718",

language = "English",

isbn = "0780397266",

series = "Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006",

publisher = "IEEE Computer Society",

pages = "131--135",

booktitle = "Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006",

address = "United States",

}

Boussaid, F, Shoushun, C & Bermak, A 2006, A novel scalable spiking pixel architecture for deep submicron CMOS technologies. in Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006., 1708718, Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006, IEEE Computer Society, pp. 131-135. https://doi.org/10.1109/dtis.2006.1708718

A novel scalable spiking pixel architecture for deep submicron CMOS technologies. / Boussaid, Farid; Shoushun, Chen; Bermak, Amine.
Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006. IEEE Computer Society, 2006. p. 131-135 1708718 (Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Shoushun, Chen

AU - Bermak, Amine

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N2 - In this paper, we propose a scalable spiking pixel architecture for deep submicron CMOS technologies. The proposed pixel architecture uniquely combines counting and memory functions into a single compact circuit, providing for in-pixel storage capability, in-pixel analog-to-digital conversion and random read-out of digital pixel values. Pixel fill-factor is better than 15% for a 50×50μm pixel fabricated using AMI 0.35μm CMOS technology. Reported experimental results validate the proposed spiking pixel architecture for the next generation of deep submicron silicon processes.

AB - In this paper, we propose a scalable spiking pixel architecture for deep submicron CMOS technologies. The proposed pixel architecture uniquely combines counting and memory functions into a single compact circuit, providing for in-pixel storage capability, in-pixel analog-to-digital conversion and random read-out of digital pixel values. Pixel fill-factor is better than 15% for a 50×50μm pixel fabricated using AMI 0.35μm CMOS technology. Reported experimental results validate the proposed spiking pixel architecture for the next generation of deep submicron silicon processes.

UR - https://www.scopus.com/pages/publications/78650344295

U2 - 10.1109/dtis.2006.1708718

DO - 10.1109/dtis.2006.1708718

M3 - Conference contribution

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SN - 0780397266

SN - 9780780397262

T3 - Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006

SP - 131

EP - 135

BT - Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006

PB - IEEE Computer Society

ER -

Boussaid F, Shoushun C, Bermak A. A novel scalable spiking pixel architecture for deep submicron CMOS technologies. In Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006. IEEE Computer Society. 2006. p. 131-135. 1708718. (Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006). doi: 10.1109/dtis.2006.1708718

A novel scalable spiking pixel architecture for deep submicron CMOS technologies

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