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A Novel Flash-Based Finite Impulse Response (FFIR) Filter Featuring Processing In-Memory (PIM) for IoT Applications

  • Cheng Yen Lee*
  • , Sunil P. Khatri
  • , Ali Ghrayeb
  • *Corresponding author for this work
  • Texas A&M University

Research output: Contribution to journal › Article › peer-review

Abstract

In this paper, we present a novel mixed-signal flashbased Finite Impulse Response (FFIR) filter architecture for Internet of Things (IoT) applications. The FFIR filter is scalable in that it can implement any filter with up to a provisioned maximum number of taps. Our FFIR filter uses flash transistors, a type of non-volatile memory (NVM) device, to perform analog computations in the current domain, achieving low power, energy, and area requirements. We implement our design using a modified 3D flash architecture, which stacks flash transistors vertically, to reduce chip area. This design is well-suited for IoT applications and other scenarios where computational resources are highly constrained. Our FFIR filter consists of several Flashbased Coefficient Multipliers (FCMs). The FIR coefficients of each FCM are stored in its constituent flash transistors, with the threshold voltage (V-t) of the flash transistors serving as a proxy for the filter coefficients. Furthermore, the impact of process, voltage, and temperature (PVT) variations is mitigated by precisely tuning the V-t of the flash transistors. The tuning of the V-t of the flash transistors can be performed either in the factory by the manufacturer (to negate process variations), or by the user in the field (to negate voltage variations or aging effects). We evaluate the tolerance of FFIR filters to manufacturing variations through Monte Carlo analysis, demonstrating robustness to process and V-DD variations. Our FFIR design achieves a significant improvement over previous approaches. Compared to Digital FIR (DFIR) filters operating at the fastest frequency (or the same frequency as our FFIR filter), the 2D implementation of our FFIR filter reduces the average power, energy, and area by 4.05 & times;, 1.95 & times;, and 2.27 & times; (2.25 & times;, 2.25 & times;, and 2.21 & times;), respectively, while the 3D implementation achieves average area improvements of 2.64 & times; (2.57 & times;). Our FFIR filters also achieve an average peak signal-to-noise ratio (PSNR) of 38.01 dB and an average measured equivalent number of bits (MENOB) of 8.87 bits. In addition, we compare our FFIR filter with state-of-the-art Analog FIR (AFIR) filters as well. Our designs demonstrate significantly improved performance, achieving average reductions of 18 & times;, 32.9 & times;, and 194 & times; in energy per tap, area, and latency, respectively, compared with four recently published AFIR works. We also show that for our FFIR design, the use of 3D flash technology reduces the overall area by approximately 12.8% compared to the use of 2D (planar) flash.
Original languageEnglish
Pages (from-to)6976-6989
Number of pages14
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume73
Issue number10
Early online dateAug 2026
DOIs
Publication statusPublished - Oct 2026

Keywords

  • Analog computation
  • Architecture
  • Computer architecture
  • Current
  • Design methodology
  • Filtering
  • Filters
  • Finite impulse response filters
  • Flash transistors
  • Internet of Things
  • Processing in-memory
  • Programming
  • Transistors
  • flash-based FIR filter

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