TY - GEN
T1 - A low-power dynamic comparator with digital calibration for reduced offset mismatch
AU - Chen, Denis Guangyin
AU - Bermak, Amine
PY - 2012
Y1 - 2012
N2 - This paper describes a fully dynamic analog comparator with digital calibration for very low offset error. In this work, we propose an off-line calibration scheme where the offset error is quantized by successive approximation. During run-time, the offset is cancelled by a digital-to-analog converter (DAC). We further improve the robustness of this cancellation by using a redundant cell to compensate for any internal mismatch within the DAC. Simulation in 0.18 um CMOS technology shows that our scheme can reduce the offset error to less than 0.86 mVrms under 1.8 V supply. The comparator consumes 1.4 pJ, and the clock to data delay is 3.5 ns.
AB - This paper describes a fully dynamic analog comparator with digital calibration for very low offset error. In this work, we propose an off-line calibration scheme where the offset error is quantized by successive approximation. During run-time, the offset is cancelled by a digital-to-analog converter (DAC). We further improve the robustness of this cancellation by using a redundant cell to compensate for any internal mismatch within the DAC. Simulation in 0.18 um CMOS technology shows that our scheme can reduce the offset error to less than 0.86 mVrms under 1.8 V supply. The comparator consumes 1.4 pJ, and the clock to data delay is 3.5 ns.
UR - https://www.scopus.com/pages/publications/84866613069
U2 - 10.1109/ISCAS.2012.6271472
DO - 10.1109/ISCAS.2012.6271472
M3 - Conference contribution
AN - SCOPUS:84866613069
T3 - ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems
SP - 1283
EP - 1286
BT - ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems
PB - IEEE Computer Society
T2 - 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Y2 - 20 May 2012 through 23 May 2012
ER -