A low power digital pixel sensor with a dynamically biased ADC

Xiajun Wu; Amine Bermak

doi:10.1109/SOCDC.2008.4815584

A low power digital pixel sensor with a dynamically biased ADC

Xiajun Wu^*, Amine Bermak

^*Corresponding author for this work

Hong Kong University of Science and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Citations (Scopus)

Abstract

In this paper,a low power CMOS image sensor using DPS scheme is proposed. A sub-threshold control unit is used in order to enable or disable the pixel level ADC depending on the photodiode sensing voltage, hence enabling to save the static power needed to operate the pixel level ADC.Results show that up to 90% power saving is achieved when compared with the conventional Digital Pixel Sensor. To compensate for the nonlinearity of the proposed time-domain ADC a clock modulation compensation scheme is proposed which can be fully implemented in digital. The sensor was implemented in 0.35um CMOS process and the sensor operation is successfully tested.

Original language	English
Title of host publication	2008 International SoC Design Conference, ISOCC 2008
Publisher	IEEE Computer Society
Pages	105-108
Number of pages	4
ISBN (Print)	9781424425990
DOIs	https://doi.org/10.1109/SOCDC.2008.4815584
Publication status	Published - 2008
Externally published	Yes
Event	2008 International SoC Design Conference, ISOCC 2008 - Busan, Korea, Republic of Duration: 24 Nov 2008 → 25 Nov 2008

Publication series

Name	s2008 International SoC Design Conference, ISOCC 2008
Volume	1

Conference

Conference	2008 International SoC Design Conference, ISOCC 2008
Country/Territory	Korea, Republic of
City	Busan
Period	24/11/08 → 25/11/08

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10.1109/SOCDC.2008.4815584

Cite this

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title = "A low power digital pixel sensor with a dynamically biased ADC",

abstract = "In this paper,a low power CMOS image sensor using DPS scheme is proposed. A sub-threshold control unit is used in order to enable or disable the pixel level ADC depending on the photodiode sensing voltage, hence enabling to save the static power needed to operate the pixel level ADC.Results show that up to 90\% power saving is achieved when compared with the conventional Digital Pixel Sensor. To compensate for the nonlinearity of the proposed time-domain ADC a clock modulation compensation scheme is proposed which can be fully implemented in digital. The sensor was implemented in 0.35um CMOS process and the sensor operation is successfully tested.",

author = "Xiajun Wu and Amine Bermak",

year = "2008",

doi = "10.1109/SOCDC.2008.4815584",

language = "English",

isbn = "9781424425990",

series = "s2008 International SoC Design Conference, ISOCC 2008",

publisher = "IEEE Computer Society",

pages = "105--108",

booktitle = "2008 International SoC Design Conference, ISOCC 2008",

address = "United States",

note = "2008 International SoC Design Conference, ISOCC 2008 ; Conference date: 24-11-2008 Through 25-11-2008",

}

Wu, X & Bermak, A 2008, A low power digital pixel sensor with a dynamically biased ADC. in 2008 International SoC Design Conference, ISOCC 2008., 4815584, s2008 International SoC Design Conference, ISOCC 2008, vol. 1, IEEE Computer Society, pp. 105-108, 2008 International SoC Design Conference, ISOCC 2008, Busan, Korea, Republic of, 24/11/08. https://doi.org/10.1109/SOCDC.2008.4815584

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AU - Bermak, Amine

PY - 2008

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N2 - In this paper,a low power CMOS image sensor using DPS scheme is proposed. A sub-threshold control unit is used in order to enable or disable the pixel level ADC depending on the photodiode sensing voltage, hence enabling to save the static power needed to operate the pixel level ADC.Results show that up to 90% power saving is achieved when compared with the conventional Digital Pixel Sensor. To compensate for the nonlinearity of the proposed time-domain ADC a clock modulation compensation scheme is proposed which can be fully implemented in digital. The sensor was implemented in 0.35um CMOS process and the sensor operation is successfully tested.

AB - In this paper,a low power CMOS image sensor using DPS scheme is proposed. A sub-threshold control unit is used in order to enable or disable the pixel level ADC depending on the photodiode sensing voltage, hence enabling to save the static power needed to operate the pixel level ADC.Results show that up to 90% power saving is achieved when compared with the conventional Digital Pixel Sensor. To compensate for the nonlinearity of the proposed time-domain ADC a clock modulation compensation scheme is proposed which can be fully implemented in digital. The sensor was implemented in 0.35um CMOS process and the sensor operation is successfully tested.

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U2 - 10.1109/SOCDC.2008.4815584

DO - 10.1109/SOCDC.2008.4815584

M3 - Conference contribution

AN - SCOPUS:69949085066

SN - 9781424425990

T3 - s2008 International SoC Design Conference, ISOCC 2008

SP - 105

EP - 108

BT - 2008 International SoC Design Conference, ISOCC 2008

PB - IEEE Computer Society

T2 - 2008 International SoC Design Conference, ISOCC 2008

Y2 - 24 November 2008 through 25 November 2008

ER -

A low power digital pixel sensor with a dynamically biased ADC

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