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A highly scalable 3D chip for binary neural network classification applications

  • Hong Kong University of Science and Technology

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper describes a 3D VLSI Chip for binary neural network classification applications. The 3D circuit includes three layers of MCM integrating 4 chips each making it a total of 12 chips integrated in a volume of (2 × 2 × 0.7)cm3. The architecture is scalable, and real-time binary neural network classifier systems could be built with one, two or all twelve chip solutions. Each basic chip includes an on-chip control unit for programming options of the neural network topology and precision. The system is modular and presents easy expansibility without requiring extra devices. Experimental test results showed that a full recall operation is obtained in less than 1.2μs for any topology with 4-bit or 8-bit precision while it is obtained in less than 2.2μs for any 16-bit precision. As a consequence the 3D chip is a very powerful reconfigurable and a multiprecision neural chip exhibiting a significant speed of 1.25 GCPS.

Original languageEnglish
Title of host publicationProceedings of the 2003 IEEE International Symposium on Circuits and Systems, ISCAS 2003
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesV685-V688
ISBN (Print)0780377613
Publication statusPublished - 2003
Externally publishedYes
Event2003 IEEE International Symposium on Circuits and Systems, ISCAS 2003 - Bangkok, Thailand
Duration: 25 May 200328 May 2003

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume5
ISSN (Print)0271-4310

Conference

Conference2003 IEEE International Symposium on Circuits and Systems, ISCAS 2003
Country/TerritoryThailand
CityBangkok
Period25/05/0328/05/03

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