A compact multi-chip-module implementation of a multi-precision neural network classifier

Amine Bermak; Dominique Martinez

doi:10.1109/ISCAS.2001.921294

A compact multi-chip-module implementation of a multi-precision neural network classifier

Amine Bermak
, Dominique Martinez

Edith Cowan University
LORIA-INRIA

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

This paper describes a novel Multi-Chip Module (MCM) digital implementation of a reconfigurable multi-precision neural network classifier. The design is based on a scalable systolic architecture with a user defined topology and arithmetic precision of the neural network. Indeed, the MCM integrates 64/32/16 neurons with a corresponding accuracy of 4/8/16-bits. A prototype has been designed and successfully tested in CMOS 0.7μm technology.

Original language	English
Pages (from-to)	249-252
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	3
DOIs	https://doi.org/10.1109/ISCAS.2001.921294
Publication status	Published - 2001
Externally published	Yes

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10.1109/ISCAS.2001.921294

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@article{ef8779b5a3b747558c46a35751081d1b,

title = "A compact multi-chip-module implementation of a multi-precision neural network classifier",

abstract = "This paper describes a novel Multi-Chip Module (MCM) digital implementation of a reconfigurable multi-precision neural network classifier. The design is based on a scalable systolic architecture with a user defined topology and arithmetic precision of the neural network. Indeed, the MCM integrates 64/32/16 neurons with a corresponding accuracy of 4/8/16-bits. A prototype has been designed and successfully tested in CMOS 0.7μm technology.",

author = "Amine Bermak and Dominique Martinez",

year = "2001",

doi = "10.1109/ISCAS.2001.921294",

language = "English",

volume = "3",

pages = "249--252",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - A compact multi-chip-module implementation of a multi-precision neural network classifier

AU - Bermak, Amine

AU - Martinez, Dominique

PY - 2001

Y1 - 2001

N2 - This paper describes a novel Multi-Chip Module (MCM) digital implementation of a reconfigurable multi-precision neural network classifier. The design is based on a scalable systolic architecture with a user defined topology and arithmetic precision of the neural network. Indeed, the MCM integrates 64/32/16 neurons with a corresponding accuracy of 4/8/16-bits. A prototype has been designed and successfully tested in CMOS 0.7μm technology.

AB - This paper describes a novel Multi-Chip Module (MCM) digital implementation of a reconfigurable multi-precision neural network classifier. The design is based on a scalable systolic architecture with a user defined topology and arithmetic precision of the neural network. Indeed, the MCM integrates 64/32/16 neurons with a corresponding accuracy of 4/8/16-bits. A prototype has been designed and successfully tested in CMOS 0.7μm technology.

UR - https://www.scopus.com/pages/publications/0034998657

U2 - 10.1109/ISCAS.2001.921294

DO - 10.1109/ISCAS.2001.921294

M3 - Article

AN - SCOPUS:0034998657

SN - 0271-4310

VL - 3

SP - 249

EP - 252

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

ER -

A compact multi-chip-module implementation of a multi-precision neural network classifier

Abstract

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