A CMOS image sensor with on chip image compression based on predictive boundary adaptation and QTD algorithm

Chen Shoushun; Amine Bermak; Wang Yan; Dominique Martinez

doi:10.1109/ICSENS.2007.4388453

A CMOS image sensor with on chip image compression based on predictive boundary adaptation and QTD algorithm

Chen Shoushun^*, Amine Bermak, Wang Yan, Dominique Martinez

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Citations (Scopus)

Abstract

This paper presents the architecture, algorithm and VLSI hardware of image acquisition, storage and compression on a single-chip CMOS image sensor. The image array is based on time domain digital pixel sensor technology equipped with nondestructive storage capability using 8-bit Static-RAM device embedded at the pixel level. An adaptive quantization scheme based on Fast Boundary Adaptation Rule (FBAR) and Differential Pulse Code Modulation (DPCM) procedure followed by an online Quadrant Tree Decomposition (QTD) processing is proposed enabling low power, robust and compact image compression processor. A prototype chip including 64 × 64 pixels, read-out and control circuitry as well as the compression processor was implemented in 0.35μm CMOS technology with a silicon area of 3.2 × 3.0mm². Simulation results show compression figures corresponding to 0.75 Bit-per-Pixel (BPP), while maintaining reasonable PSNR levels.

Original language	English
Title of host publication	The 6th IEEE Conference on SENSORS, IEEE SENSORS 2007
Pages	531-534
Number of pages	4
DOIs	https://doi.org/10.1109/ICSENS.2007.4388453
Publication status	Published - 2007
Externally published	Yes
Event	6th IEEE Conference on SENSORS, IEEE SENSORS 2007 - Atlanta, GA, United States Duration: 28 Oct 2007 → 31 Oct 2007

Publication series

Name	Proceedings of IEEE Sensors

Conference

Conference	6th IEEE Conference on SENSORS, IEEE SENSORS 2007
Country/Territory	United States
City	Atlanta, GA
Period	28/10/07 → 31/10/07

Access to Document

10.1109/ICSENS.2007.4388453

Cite this

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title = "A CMOS image sensor with on chip image compression based on predictive boundary adaptation and QTD algorithm",

abstract = "This paper presents the architecture, algorithm and VLSI hardware of image acquisition, storage and compression on a single-chip CMOS image sensor. The image array is based on time domain digital pixel sensor technology equipped with nondestructive storage capability using 8-bit Static-RAM device embedded at the pixel level. An adaptive quantization scheme based on Fast Boundary Adaptation Rule (FBAR) and Differential Pulse Code Modulation (DPCM) procedure followed by an online Quadrant Tree Decomposition (QTD) processing is proposed enabling low power, robust and compact image compression processor. A prototype chip including 64 × 64 pixels, read-out and control circuitry as well as the compression processor was implemented in 0.35μm CMOS technology with a silicon area of 3.2 × 3.0mm2. Simulation results show compression figures corresponding to 0.75 Bit-per-Pixel (BPP), while maintaining reasonable PSNR levels.",

author = "Chen Shoushun and Amine Bermak and Wang Yan and Dominique Martinez",

year = "2007",

doi = "10.1109/ICSENS.2007.4388453",

language = "English",

isbn = "1424412617",

series = "Proceedings of IEEE Sensors",

pages = "531--534",

booktitle = "The 6th IEEE Conference on SENSORS, IEEE SENSORS 2007",

note = "6th IEEE Conference on SENSORS, IEEE SENSORS 2007 ; Conference date: 28-10-2007 Through 31-10-2007",

}

Shoushun, C, Bermak, A, Yan, W & Martinez, D 2007, A CMOS image sensor with on chip image compression based on predictive boundary adaptation and QTD algorithm. in The 6th IEEE Conference on SENSORS, IEEE SENSORS 2007., 4388453, Proceedings of IEEE Sensors, pp. 531-534, 6th IEEE Conference on SENSORS, IEEE SENSORS 2007, Atlanta, GA, United States, 28/10/07. https://doi.org/10.1109/ICSENS.2007.4388453

A CMOS image sensor with on chip image compression based on predictive boundary adaptation and QTD algorithm. / Shoushun, Chen; Bermak, Amine; Yan, Wang et al.
The 6th IEEE Conference on SENSORS, IEEE SENSORS 2007. 2007. p. 531-534 4388453 (Proceedings of IEEE Sensors).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Shoushun, Chen

AU - Bermak, Amine

AU - Yan, Wang

AU - Martinez, Dominique

PY - 2007

Y1 - 2007

N2 - This paper presents the architecture, algorithm and VLSI hardware of image acquisition, storage and compression on a single-chip CMOS image sensor. The image array is based on time domain digital pixel sensor technology equipped with nondestructive storage capability using 8-bit Static-RAM device embedded at the pixel level. An adaptive quantization scheme based on Fast Boundary Adaptation Rule (FBAR) and Differential Pulse Code Modulation (DPCM) procedure followed by an online Quadrant Tree Decomposition (QTD) processing is proposed enabling low power, robust and compact image compression processor. A prototype chip including 64 × 64 pixels, read-out and control circuitry as well as the compression processor was implemented in 0.35μm CMOS technology with a silicon area of 3.2 × 3.0mm2. Simulation results show compression figures corresponding to 0.75 Bit-per-Pixel (BPP), while maintaining reasonable PSNR levels.

AB - This paper presents the architecture, algorithm and VLSI hardware of image acquisition, storage and compression on a single-chip CMOS image sensor. The image array is based on time domain digital pixel sensor technology equipped with nondestructive storage capability using 8-bit Static-RAM device embedded at the pixel level. An adaptive quantization scheme based on Fast Boundary Adaptation Rule (FBAR) and Differential Pulse Code Modulation (DPCM) procedure followed by an online Quadrant Tree Decomposition (QTD) processing is proposed enabling low power, robust and compact image compression processor. A prototype chip including 64 × 64 pixels, read-out and control circuitry as well as the compression processor was implemented in 0.35μm CMOS technology with a silicon area of 3.2 × 3.0mm2. Simulation results show compression figures corresponding to 0.75 Bit-per-Pixel (BPP), while maintaining reasonable PSNR levels.

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M3 - Conference contribution

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SN - 1424412617

SN - 9781424412617

T3 - Proceedings of IEEE Sensors

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BT - The 6th IEEE Conference on SENSORS, IEEE SENSORS 2007

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Y2 - 28 October 2007 through 31 October 2007

ER -

A CMOS image sensor with on chip image compression based on predictive boundary adaptation and QTD algorithm

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