A 96 × 64 Intelligent digital pixel array with extended binary stochastic arithmetic

Tarik Hammadou; Magnus Nilson; Amine Bermak; Philip Ogunbona

A 96 × 64 Intelligent digital pixel array with extended binary stochastic arithmetic

Tarik Hammadou^*
, Magnus Nilson
, Amine Bermak
, Philip Ogunbona

^*Corresponding author for this work

Motorola
Hong Kong University of Science and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

12 Citations (Scopus)

Abstract

A chip architecture that integrates an optical sensor and a pixel level processing element based on binary stochastic arithmetic is proposed. The optical sensor is formed by an array of fully connected pixels, and each pixel contains a sensing element and a Pulse Frequency Modulator (PFM) converting the incident light to bit streams of identical pulses. The processing element is based on binary stochastic arithmetic to perform signal processing operations on the focal plane VLSI circuit. A 96 × 64 CMOS image sensor is fabricated using 0.5μm CMOS technology and achieves 29 × 29μm pixel size at 15% fill factor.

Original language	English
Title of host publication	Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, ISCAS 2003
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	IV772-IV775
ISBN (Print)	0780377613
Publication status	Published - 2003
Externally published	Yes
Event	2003 IEEE International Symposium on Circuits and Systems, ISCAS 2003 - Bangkok, Thailand Duration: 25 May 2003 → 28 May 2003

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	4
ISSN (Print)	0271-4310

Conference

Conference	2003 IEEE International Symposium on Circuits and Systems, ISCAS 2003
Country/Territory	Thailand
City	Bangkok
Period	25/05/03 → 28/05/03

Cite this

Hammadou, T., Nilson, M., Bermak, A., & Ogunbona, P. (2003). A 96 × 64 Intelligent digital pixel array with extended binary stochastic arithmetic. In Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, ISCAS 2003 (pp. IV772-IV775). (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 4). Institute of Electrical and Electronics Engineers Inc..

Hammadou, Tarik ; Nilson, Magnus ; Bermak, Amine et al. / A 96 × 64 Intelligent digital pixel array with extended binary stochastic arithmetic. Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, ISCAS 2003. Institute of Electrical and Electronics Engineers Inc., 2003. pp. IV772-IV775 (Proceedings - IEEE International Symposium on Circuits and Systems).

@inproceedings{6fea00f37f2346dfac91e95f06830442,

title = "A 96 {\texttimes} 64 Intelligent digital pixel array with extended binary stochastic arithmetic",

abstract = "A chip architecture that integrates an optical sensor and a pixel level processing element based on binary stochastic arithmetic is proposed. The optical sensor is formed by an array of fully connected pixels, and each pixel contains a sensing element and a Pulse Frequency Modulator (PFM) converting the incident light to bit streams of identical pulses. The processing element is based on binary stochastic arithmetic to perform signal processing operations on the focal plane VLSI circuit. A 96 {\texttimes} 64 CMOS image sensor is fabricated using 0.5μm CMOS technology and achieves 29 {\texttimes} 29μm pixel size at 15\% fill factor.",

author = "Tarik Hammadou and Magnus Nilson and Amine Bermak and Philip Ogunbona",

year = "2003",

language = "English",

isbn = "0780377613",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "IV772--IV775",

booktitle = "Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, ISCAS 2003",

address = "United States",

note = "2003 IEEE International Symposium on Circuits and Systems, ISCAS 2003 ; Conference date: 25-05-2003 Through 28-05-2003",

}

Hammadou, T, Nilson, M, Bermak, A & Ogunbona, P 2003, A 96 × 64 Intelligent digital pixel array with extended binary stochastic arithmetic. in Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, ISCAS 2003. Proceedings - IEEE International Symposium on Circuits and Systems, vol. 4, Institute of Electrical and Electronics Engineers Inc., pp. IV772-IV775, 2003 IEEE International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, 25/05/03.

A 96 × 64 Intelligent digital pixel array with extended binary stochastic arithmetic. / Hammadou, Tarik; Nilson, Magnus; Bermak, Amine et al.
Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, ISCAS 2003. Institute of Electrical and Electronics Engineers Inc., 2003. p. IV772-IV775 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 4).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Hammadou, Tarik

AU - Nilson, Magnus

AU - Bermak, Amine

AU - Ogunbona, Philip

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N2 - A chip architecture that integrates an optical sensor and a pixel level processing element based on binary stochastic arithmetic is proposed. The optical sensor is formed by an array of fully connected pixels, and each pixel contains a sensing element and a Pulse Frequency Modulator (PFM) converting the incident light to bit streams of identical pulses. The processing element is based on binary stochastic arithmetic to perform signal processing operations on the focal plane VLSI circuit. A 96 × 64 CMOS image sensor is fabricated using 0.5μm CMOS technology and achieves 29 × 29μm pixel size at 15% fill factor.

AB - A chip architecture that integrates an optical sensor and a pixel level processing element based on binary stochastic arithmetic is proposed. The optical sensor is formed by an array of fully connected pixels, and each pixel contains a sensing element and a Pulse Frequency Modulator (PFM) converting the incident light to bit streams of identical pulses. The processing element is based on binary stochastic arithmetic to perform signal processing operations on the focal plane VLSI circuit. A 96 × 64 CMOS image sensor is fabricated using 0.5μm CMOS technology and achieves 29 × 29μm pixel size at 15% fill factor.

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M3 - Conference contribution

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SN - 0780377613

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - IV772-IV775

BT - Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, ISCAS 2003

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2003 IEEE International Symposium on Circuits and Systems, ISCAS 2003

Y2 - 25 May 2003 through 28 May 2003

ER -

Hammadou T, Nilson M, Bermak A, Ogunbona P. A 96 × 64 Intelligent digital pixel array with extended binary stochastic arithmetic. In Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, ISCAS 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. IV772-IV775. (Proceedings - IEEE International Symposium on Circuits and Systems).

A 96 × 64 Intelligent digital pixel array with extended binary stochastic arithmetic

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