A 1.5-2.0 TOPS/W 2T-Pixel CMOS Imager With Programmable In-Pixel Multi-Bit Feature Extraction

As the demand for embedding edge intelligence in vision systems continues to grow, future image sensors must become smarter and capable of performing efficient on-chip computation. This paper presents a hardware-friendly computational CMOS image sensor ((CIS)-I-2) that performs signed analog-domain multi-bit convolution directly within the pixel array to enable energy-efficient embedded vision. The proposed (CIS)-I-2 uses a compact two-transistor (2T) pixel-without in-pixel weight memory or capacitors-while maintaining a 43% fill factor. By leveraging programmable column link switches and shared CTIA+SS-ADC channels, the system supports up to eight programmable convolution kernels per frame without requiring intermediate SRAM or DAC for partial-sum storage. Fabricated in a standard 0.18 & micro;m CMOS process, the prototype achieves 1.5-2.0 TOPS/W performance (normalized to 1-bit), corresponding to 14-112 fps at 61.8-82.4 & micro;W total chip power. A vision system incorporating the proposed (CIS)-I-2 demonstrates validation accuracy of 96.7% for handwritten digit recognition and 94.2% for hand gesture recognition. These results confirm the feasibility of this approach for low-power, high-density feature extraction, making it well suited for next-generation edge AI applications.