@inproceedings{0566f39dd549458788b30e7803e3eafb,
title = "A 14-bit 70MS/s pipeline ADC with power-efficient back-end stages",
abstract = "A 14-bit SHA-less pipeline ADC based on 2.5-bit per stage architecture is proposed. Implemented in TSMC 0.18μm CMOS process, the proposed ADC achieves an ENOB of 11.34-bits and consumes 41 mW power at 70 MS/s thereby achieving an FOM of 226fJ/conversion-step which compares favorably with state-of-the-art work. The low-power consumption is attributed to the careful design of back-end stages based on a novel gain-boosting recycling folded-cascode amplifier.",
keywords = "Gain boosting, Recycling folded cascode amplifier, SHA-less pipeline ADC",
author = "Moaaz Ahmed and Fang Tang and Amine Bermak",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 ; Conference date: 01-06-2015 Through 04-06-2015",
year = "2015",
month = sep,
day = "30",
doi = "10.1109/EDSSC.2015.7285073",
language = "English",
series = "Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "154--157",
booktitle = "Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015",
address = "United States",
}